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EM65565A
65 COM/ 132 SEG STN LCD Driver
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
June 2005
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM Windows is a trademark of Microsoft Corporation ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation
Copyright (c) 2005 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8223 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai Corporation, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 021 5080-3866 Fax: +86 021 5080-4600
Contents
Contents
1 2 3 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 Pin Configuration ...................................................................................................... 3 3.1 4 5 6 Pin Dimensions ...................................................................................................4 3.2 Mark Dimensions ................................................................................................4 Pin Description.......................................................................................................... 8 Block Diagram ..........................................................................................................11 Functional Description ........................................................................................... 12 6.1 The MPU Interface............................................................................................12
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.1.18 6.1.19 6.1.20 6.1.21 Selecting the Interface Type..............................................................................12 Chip Select ........................................................................................................13 Accessing the DDRAM and the Internal Registers ...........................................13 Busy Flag ..........................................................................................................13 Page Address Circuit.........................................................................................14 Line Address Circuit ..........................................................................................14 Column Addresses Circuit.................................................................................15 Display Data RAM (DDRAM) ............................................................................15 Display Data Latch Circuit .................................................................................16 Oscillator Circuit ................................................................................................17 Display Timing Generator Circuit ......................................................................17 Common Output Status Select Circuit...............................................................18 LCD Driver Circuits............................................................................................18 Power Supply Circuits .......................................................................................18 Step-up Voltage Circuit......................................................................................19 Voltage Regulator Circuit...................................................................................19 Liquid Crystal Voltage Generator Circuit ...........................................................21 Power Supply Control Circuit ............................................................................21 Internal Power Supply Shutdown Command Sequence ..................................22 Reference Circuit Example ...............................................................................22 Reset Circuit......................................................................................................24
Product Specification (V1.0) 06.06.2005
* iii
Contents
7
Commands............................................................................................................... 25 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Display ON/OFF................................................................................................26 Set Display Start Line........................................................................................26 Set Column Address .........................................................................................26 Set Page Address .............................................................................................27 Select ADC........................................................................................................27 Write Display Data ............................................................................................27 Read Display Data ............................................................................................27 Read Status ......................................................................................................28 Read-Modify-Write ............................................................................................28
7.10 End....................................................................................................................28 7.11 Reset.................................................................................................................29 7.12 Display All Points ON ........................................................................................29 7.13 Display Normal/Reverse ...................................................................................29 7.14 LCD Bias Set ....................................................................................................29 7.15 Common Output Mode Select...........................................................................29 7.16 Power Controller Set.........................................................................................30 7.17 V0 Voltage Regulator Internal Resistor Ratio Set .............................................30 7.18 Electronic Volume .............................................................................................30 7.19 Static Indicator ..................................................................................................31 7.20 Power Save.......................................................................................................31 7.21 NOP ..................................................................................................................32 8 9 10 7.22 Test ...................................................................................................................32 Absolute Maximum Ratings ................................................................................... 34 DC Characteristics .................................................................................................. 34 Timing Diagram ....................................................................................................... 36 10.1 System Bus Read/Write Timing I (80-Series MPU)...........................................36 10.2 System Bus Read/Write Timing (68-Series MPU).............................................37 10.3 Serial Interface..................................................................................................38 10.4 Display Control Output Timing ..........................................................................38 11 12 10.5 Reset Timing .....................................................................................................39 Application Circuit .................................................................................................. 39 Recommended Cog Ito Traces Resistor ............................................................... 41 12.1 Tray Information ................................................................................................42 12.2 Tray Outline Dimension.....................................................................................42
iv *
Product Specification (V1.0) 06.06.2005
Contents
Specification Revision History
Doc. Version 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Initial version Added /RST ITO trace resistor and display off current Modified the VRS and VR pin description Modified the VREG rating Added mark appearance diagram Removed the thermal gradient description Modified the VRS No. of Pins 3 2 Revision Description Date 2003/01/13 2003/06/18 2003/09/17 2003/10/03 2003/10/24 2003/12/16 2004/09/09 2004/04/01 2004/05/28
Modified the Vreg min. & max. value Added Tray Information Added Test Pin description 1. Added VREG Temperature coefficient 2. Added the recommended Type of Capacitor for the Application Circuit. 3. Modified the VREG rating
1.0
2005/06/06
Product Specification (V1.0) 06.06.2005
*v
Contents
vi *
Product Specification (V1.0) 06.06.2005
EM65565A
65 COM/132SEG STN LCD Driver
1
General Description
The EM65565A is a 65 Common 132 Segment dot matrix Liquid Crystal Display (LCD) driver LSI, which can be connected directly to a microprocessor bus, and can select an 8-bit parallel or serial data input interface. The EM65565A IC contains 65x132 bits of display data RAM (DDRAM) and there is a one-to-one correspondence between the LCD panel pixels and the internal RAM bits. The EM65565A IC can drive a 65x132 dot display, and the capacity of the display can be extended by master/slave structures between ICs. This device has minimal power consumption since no external operating clock is necessary for the DDRAM read/write operation. Furthermore, each IC has a built-in low-power LCD driver power supply, on-chip resistors for LCD driver power voltage adjustment and a display clock RC oscillator circuit, these and all the other features combined make the EM65565A IC suitable for lowest power display systems with the fewest components for high-performance portable devices.
2
Features
Direct display of RAM data through the DDRAM RAM bit data: "0" : Illuminated "1" : Non-illuminated
RAM capacity: 65x132 = 8,580 bits Display driver circuits: 65 common output and 132 segment outputs High-speed 8-bit MPU interface (80-series and 68-series) / Serial interfaces are supported Abundant command functions: display data Read/Write, display ON/OFF, status read, Normal/Reverse display mode, page address set, display start line set, column address set, display all points ON/OFF, LCD bias set, electronic volume, read-modify-write, segment driver direction select, power saver, static indicator, common output status select, V0 voltage regulation internal resistor ratio set. Built-in Static drive circuit for indicators Built-in Low-power LCD power supply circuit Built-in Booster circuit, with Boost ratios of two/three/four/five times, where the step-up voltage reference power supply can be input externally Built-in High-accuracy voltage adjustment circuit (external input) Built-in V0 voltage regulator resistors Built-in V1 to V4 voltage divider resistors Built-in electronic volume function
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
*1
EM65565A
65 COM/132SEG STN LCD Driver Voltage follower Internal RC oscillator circuit (external clock can also be input) Extreme low power consumption Power supply, operable on the low 1.8V - Logic power supply: VDD - VSS = 2.4V to 3.3V - Boost reference voltage: VCI = 2.4V to 3.3V - LCD driver power supply: VLCD = V0 - VSS = 4.5V to 12.0V Non-resistant to light or radiation Package (Ordering information)
Part Number EM65565AAGH Package Gold bumped chip Description NA Package Information Page 5
Note: The EM65565A series has the following sub-codes, depending on their shapes. H: Bare chip (Aluminum pad without bump); GH: Gold bumped chip F: COF package; T: TAB (TCP) package Example: EM65565AAGH chip EM65565A: Elan number; A: Package Version; GH: Gold bumped
2*
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
3
Pin Configuration
309
1
293
292
D-Left Mark
22 23
U-Left Mark
45 46
67 68
89 90
D-Right Mark
U-Right Mark
111
129
112
128
Fig. 1 Pin Configuration
NOTE With the Elan logo at the upper left corner, Pin 1 is at the bottom left corner, viewed lengthwise.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
*3
EM65565A
65 COM/132SEG STN LCD Driver
3.1 Pin Dimensions
Item Chip size Bump Size Pad Pitch Die thickness (excluding bumps) Bump Height Minimum Bump Gap Coordinate Origin Pad No. 1 ~ 309 Size X 10570 43 60 (min.) 525 25 All Pad 17 3 (within die) 17 Chip center Y 1210 60 m Unit
3.2 Mark Dimensions
Mark U-Left D-Left Coordinate (X,Y) -4714.25 , 124.55 -4714.25 , -215.4 Mark U-Right D-Right Coordinate (X,Y) 4544.1 , 124.55 4544.1 , -215.4
Mark Appearance
50m
50 m
4*
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver Pad Coordinates Table
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad Name NC1 NC2 NC3 NC4 NC5 TEST1 TEST2 TEST3 FRS FR FR DCLK /BCT VSS VSS /CS1 CS2 VDD /RST D/I VSS /WR /RD VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD VSS VDD VDD VDD VDD VDD VDD VDD VCI VCI VCI VSS VSS VSS VSS VSS Coordinate (X,Y) -4861.2 , -485.0 -4779.7 , -485.0 -4698.2 , -485.0 -4616.7 , -485.0 -4535.2 , -485.0 -4453.7 , -485.0 -4372.2 , -485.0 -4290.7 , -485.0 -4209.2 , -485.0 -4127.7 , -485.0 -4046.2 , -485.0 -3964.7 , -485.0 -3883.2 , -485.0 -3801.7 , -485.0 -3720.2 , -485.0 -3638.7 , -485.0 -3557.2 , -485.0 -3475.7 , -485.0 -3394.2 , -485.0 -3312.7 , -485.0 -3231.2 , -485.0 -3149.7 , -485.0 -2877.3 , -485.0 -2795.8 , -485.0 -2714.3 , -485.0 -2632.8 , -485.0 -2551.3 , -485.0 -2469.8 , -485.0 -2388.3 , -485.0 -2306.8 , -485.0 -2225.3 , -485.0 -2143.8 , -485.0 -2062.3 , -485.0 -1980.8 , -485.0 -1899.3 , -485.0 -1817.8 , -485.0 -1736.3 , -485.0 -1654.8 , -485.0 -1573.3 , -485.0 -1491.8 , -485.0 -1410.3 , -485.0 -1328.8 , -485.0 -1247.3 , -485.0 -1165.8 , -485.0 -1084.3 , -485.0 , -811.9 -485.0 , -730.4 -485.0 , -648.9 -485.0 , -567.4 -485.0 , -485.9 -485.0 Pin No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name VSS VSS VSS VSS VSS VSS VOUT VOUT CAP4+ CAP4+ CAP4+ CAP3+ CAP3+ CAP3+ CAP1CAP1CAP1CAP1+ CAP1+ CAP1+ CAP2+ CAP2+ CAP2+ CAP2CAP2CAP2VDD VRS VRS VSS V1 V1 V1 V2 V2 V2 V3 V3 V3 V4 V4 V4 V0 V0 V0 VR VR VR VSS VSS Coordinate (X,Y) -404.4 , -485.0 -322.9 , -485.0 -241.4 , -485.0 -159.9 , -485.0 -78.4 , -485.0 3.1 , -485.0 84.6 , -485.0 166.1 , -485.0 247.6 , -485.0 329.1 , -485.0 410.6 , -485.0 492.1 , -485.0 573.6 , -485.0 655.1 , -485.0 736.6 , -485.0 818.1 , -485.0 899.6 , -485.0 1172.0 , -485.0 1253.5 , -485.0 1335.0 , -485.0 1416.5 , -485.0 1498.0 , -485.0 1579.5 , -485.0 1661.0 , -485.0 1742.5 , -485.0 1824.0 , -485.0 1905.5 , -485.0 1987.0 , -485.0 2068.5 , -485.0 2150.0 , -485.0 2231.5 , -485.0 2313.0 , -485.0 2394.5 , -485.0 2476.0 , -485.0 2557.5 , -485.0 2639.0 , -485.0 2720.5 , -485.0 2802.0 , -485.0 2883.5 , -485.0 3155.9 , -485.0 3237.4 , -485.0 3318.9 , -485.0 3400.4 , -485.0 3481.9 , -485.0 3563.4 , -485.0 3644.9 , -485.0 3726.4 , -485.0 3807.9 , -485.0 3889.4 , -485.0 3970.9 , -485.0
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
*5
EM65565A
65 COM/132SEG STN LCD Driver
Pin No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name VDD M/S DCLKS VSS MPUS P/S VDD /PCT VSS IRS VDD COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 SEG3 SEG4 SEG5
Coordinate (X,Y) , 4052.4 -485.0 , 4133.9 -485.0 , 4215.4 -485.0 , 4296.9 -485.0 , 4378.4 -485.0 , 4459.9 -485.0 , 4541.4 -485.0 , 4622.9 -485.0 , 4704.4 -485.0 , 4785.9 -485.0 , 4867.4 -485.0 , 5165.0 -480.0 , 5165.0 -420.0 , 5165.0 -360.0 , 5165.0 -300.0 , 5165.0 -240.0 , 5165.0 -180.0 , 5165.0 -120.0 , 5165.0 -60.0 , 5165.0 0.0 , 5165.0 60.0 , 5165.0 120.0 , 5165.0 180.0 , 5165.0 240.0 , 5165.0 300.0 , 5165.0 360.0 , 5165.0 420.0 , 5165.0 480.0 , 4889.9 485.0 , 4829.9 485.0 , 4769.9 485.0 , 4709.9 485.0 , 4649.9 485.0 , 4589.9 485.0 , 4529.9 485.0 , 4469.9 485.0 , 4409.9 485.0 , 4349.9 485.0 , 4289.9 485.0 , 4229.9 485.0 , 4169.9 485.0 , 4109.9 485.0 , 4049.9 485.0 , 3989.9 485.0 , 3929.9 485.0 , 3869.9 485.0 , 3809.9 485.0 , 3749.9 485.0 , 3689.9 485.0 , 3629.9 485.0
Pin No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55
Coordinate (X,Y) , 3569.9 485.0 , 3509.9 485.0 , 3449.9 485.0 , 3389.9 485.0 , 3329.9 485.0 , 3269.9 485.0 , 3209.9 485.0 , 3149.9 485.0 , 3089.9 485.0 , 3029.9 485.0 , 2969.9 485.0 , 2909.9 485.0 , 2849.9 485.0 , 2789.9 485.0 , 2729.9 485.0 , 2669.9 485.0 , 2609.9 485.0 , 2549.9 485.0 , 2489.9 485.0 , 2429.9 485.0 , 2369.9 485.0 , 2309.9 485.0 , 2249.9 485.0 , 2189.9 485.0 , 2129.9 485.0 , 2069.9 485.0 , 2009.9 485.0 , 1949.9 485.0 , 1889.9 485.0 , 1829.9 485.0 , 1769.9 485.0 , 1709.9 485.0 , 1649.9 485.0 , 1589.9 485.0 , 1529.9 485.0 , 1469.9 485.0 , 1409.9 485.0 , 1349.9 485.0 , 1289.9 485.0 , 1229.9 485.0 , 1169.9 485.0 , 1109.9 485.0 , 1049.9 485.0 , 989.9 485.0 , 929.9 485.0 , 869.9 485.0 , 809.9 485.0 , 749.9 485.0 , 689.9 485.0 , 629.9 485.0
6*
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
Pin No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105
Coordinate (X,Y) , 569.9 485.0 , 509.9 485.0 , 449.9 485.0 , 389.9 485.0 , 329.9 485.0 , 269.9 485.0 , 209.9 485.0 , 149.9 485.0 , 89.9 485.0 , 29.9 485.0 , -30.1 485.0 , -90.1 485.0 , -150.1 485.0 , -210.1 485.0 , -270.1 485.0 , -330.1 485.0 , -390.1 485.0 , -450.1 485.0 , -510.1 485.0 , -570.1 485.0 , -630.1 485.0 , -690.1 485.0 , -750.1 485.0 , -810.1 485.0 , -870.1 485.0 , -930.1 485.0 , -990.1 485.0 -1050.1 , 485.0 -1110.1 , 485.0 -1170.1 , 485.0 -1230.1 , 485.0 -1290.1 , 485.0 -1350.1 , 485.0 -1410.1 , 485.0 -1470.1 , 485.0 -1530.1 , 485.0 -1590.1 , 485.0 -1650.1 , 485.0 -1710.1 , 485.0 -1770.1 , 485.0 -1830.1 , 485.0 -1890.1 , 485.0 -1950.1 , 485.0 -2010.1 , 485.0 -2070.1 , 485.0 -2130.1 , 485.0 -2190.1 , 485.0 -2250.1 , 485.0 -2310.1 , 485.0 -2370.1 , 485.0
Pin No 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55
Coordinate (X,Y) -2430.1 , 485.0 -2490.1 , 485.0 -2550.1 , 485.0 -2610.1 , 485.0 -2670.1 , 485.0 -2730.1 , 485.0 -2790.1 , 485.0 -2850.1 , 485.0 -2910.1 , 485.0 -2970.1 , 485.0 -3030.1 , 485.0 -3090.1 , 485.0 -3150.1 , 485.0 -3210.1 , 485.0 -3270.1 , 485.0 -3330.1 , 485.0 -3390.1 , 485.0 -3450.1 , 485.0 -3510.1 , 485.0 -3570.1 , 485.0 -3630.1 , 485.0 -3690.1 , 485.0 -3750.1 , 485.0 -3810.1 , 485.0 -3870.1 , 485.0 -3930.1 , 485.0 -3990.1 , 485.0 -4050.1 , 485.0 -4110.1 , 485.0 -4170.1 , 485.0 -4230.1 , 485.0 -4290.1 , 485.0 -4350.1 , 485.0 -4410.1 , 485.0 -4470.1 , 485.0 -4530.1 , 485.0 -4590.1 , 485.0 -4650.1 , 485.0 -4710.1 , 485.0 -4770.1 , 485.0 -4830.1 , 485.0 -4890.1 , 485.0 -5165.0 , 480.0 -5165.0 , 420.0 -5165.0 , 360.0 -5165.0 , 300.0 -5165.0 , 240.0 -5165.0 , 180.0 -5165.0 , 120.0 -5165.0 , 60.0
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
*7
EM65565A
65 COM/132SEG STN LCD Driver
Pin No 301 302 303 304 305 306 307 308 309
Pad Name COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
-5165.0 -5165.0 -5165.0 -5165.0 -5165.0 -5165.0 -5165.0 -5165.0 -5165.0
Coordinate (X,Y) , 0.0 , -60.0 , -120.0 , -180.0 , -240.0 , -300.0 , -360.0 , -420.0 , -480.0
Pin No
Pad Name
Coordinate (X,Y)
4
Pin Description
Pin Name VDD VSS VCI VRS I/O - - I I Function Power supply shared with the MPU terminal VCC Power supply, 0V terminal connected to the system GND Reference power supply for the step-up voltage circuit for the liquid crystal drive. Externally input VREG power supply for the LCD power supply voltage regulator. If an internal voltage regulator is used, VRS must be floating. Multi-level power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divider or through changing the impedance using an Op. Amp. Voltage levels are determined based on V0, and must maintain the relative magnitudes shown below. V0V1V2V3V4VSS Master operation: When the power supply turns ON, the internal power supply circuits generate the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. 1/9 bias V1 V2 V3 V4 CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4+ VOUT VR O O O O O O I/O O 8/9xV0 7/9xV0 2/9xV0 1/9xV0 1/7 bias 6/7xV0 5/7xV0 2/7xV0 1/7xV0
V0 V1 V2 V3 V4 I/O
Capacitor 1 positive connection pin for the voltage converter Capacitor 1 negative connection pin for the voltage converter Capacitor 2 positive connection pin for the voltage converter Capacitor 2 negative connection pin for the voltage converter Capacitor 3 positive connection pin for the voltage converter Capacitor 4 positive connection pin for the voltage converter DC/DC voltage converter input/output pin. Connect a capacitor between this terminal and VSS Output voltage regulator terminal. This is only enabled (IRS = "L") when the V0 voltage regulator internal resistor is not used. When the V0 voltage regulator internal resistor is used (IRS = "H"), this pin must be floating. 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When chip select is inactive, D0 to D7 are set to high impedance. When serial interface is selected (P/S = "L"), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
D7 to D0
I/O
8*
EM65565A
65 COM/132SEG STN LCD Driver
Pin Name I/O D/I D/I I H L /RST /CS1 CS2 /RD (E) /WR (R/W) MPUS I I I I D0 to D7 Display data Instruction (Command) Function Determines whether the data bits are data or instruction (command).
I
When /RST is set to "L," the settings are initialized. Chip select signal. When /CS1 = "L" and CS2 = "H," then the chip select CS2 becomes active, and data/command I/O is enabled. Enable clock signal input for the 68-series MPU, active high. Active low input pin for the 80-series MPU /RD signal Read/Write control signal with 68-series MPU. R/W="H": Read R/W="L": Write Active low input pin for the 80 series MPU /WR signal. MPU interface switch terminal. MPUS = "H": 68-series MPU interface MPUS = "L": 80-series MPU interface Selects whether Parallel or Serial data input interface. P/S = "H": Parallel data input interface P/S = "L": Serial data input interface The following applies depending on the P/S status: P/S Data/Command Data D0 to D7 D7 (SI) Read/Write Serial Clock /RD, /WR Write only D6 (SCL) H L D/I D/I
P/S
I
DCLKS
I
When P/S = "L", D0 to D5 are HZ. D0 to D5 may be "H", "L" or Open. RD (E) and WR (P/W) are fixed to either "H" or "L". With serial data input, RAM display data reading is not supported. Terminal used to select whether to enable or disable the display clock internal oscillator circuit. DCLKS = "H": Internal oscillator circuit is enabled DCLKS = "L": Internal oscillator circuit is disabled (requires external input) When DCLKS = "L", input the display clock through the DCLK terminal. M/S = "H": Master operation M/S = "L": Slave operation The following is true, depending on the M/S and DCLKS status:
M/S DCLKS Oscillator circuit Power Supply DCLK FR Circuit FRS /BCT
M/S
I
H L
H L H L
Enable Disable Disable Disable
Enable Enable Disable Disable
O I I I
O O I I
O O O O
O O I I
O : Output I : Input Display clock input terminal. The following is true depending on the M/S and DCLKS status. M/S DCLKS DCLK I/O H L H L H L DCLK Output Input Input Input
When the EM65565A chips are used in master/slave mode, the various DCLK terminals must be connected. Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
Pin Name I/O Function Liquid crystal alternating current signal I/O terminal. M/S = "H" : Output M/S = "L" : Input When the EM65565A Series IC is used in master/slave mode, the various FR terminals must be connected. LCD blanking control terminal. M/S = "H" : Output, M/S = "L" : Input When the EM65565A chip is used in master/slave mode, the various /BCT terminals must be connected. Output terminal for the static drive. This terminal is only enabled when the static indicator display is ON in master operation mode, and is used in conjunction with the FR terminal. Terminal used to select the resistors for the V0 voltage level adjustment. IRS = "H" : Use the internal resistors IRS = "L" : Do not use the internal resistors. The V0 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either "H" or "L" when the slave operation mode is selected. Power control terminal for the liquid crystal drive power supply circuit. /PCT = "H" : Normal mode /PCT = "L" : High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either "H" or "L" when the slave operation mode is selected. Liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from V0, V2, V3, and VSS. RAM DATA SEG0 to SEG131 O H H L L Power Save & Display OFF H L H L -FR V0 VSS V2 V3 VSS Output Voltage Normal Display Reverse Display V2 V3 V0 VSS
FR
I/O
/BCT
I/O
FRS
O
IRS
I
/PCT
I
LCD common drive outputs. Through a combination of the contents of the scan data and with the FR signal, a single level is selected from V0, V1, V4, and VSS. COM 0 to COM 63 O Scan Data H H L L Power Save FR H L H L -Output Voltage VSS V0 V1 V4 VSS
COMS TEST1~3
O I/O
Common output terminal for the indicator. This terminal outputs the same signal. Leave this open if it is not used. When in master/slave mode, the same signal is output by both master and slave. For IC testing, should be floating
10 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
5
Block Diagram
CAP4+ CAP3+ CAP2+ CAP1+ CAP2CAP1/DSPOF
DCLK
DCLKS
Instruction Decoder
Display Start Line Register Line Counter Line Address Decoder Column Address decoder Column Address counter Column Address register
LCD Driver Circuit
Data Latch
/CS1 CS2 /RST D/I P/S /RD, /WR (E, R/W) D7(SI) D6(SCL) D0-D5
MPU Interface
Status Register
Common counter
Bus Holder
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
/PCT
VOUT
FRS
M/S
VRS
IRS
VCI
FR
VR
Power Supply Circuit
Oscillator Circuit
Display Timing Generator
VDD,VSS,V1,V2,V3,V4,V5 SEG0~SEG131 COM0~COM63 COMS
Display Data RAM (DDRAM) 8580-bits
I/O Buffer Page Address Circuit
Figure 1 System Block Diagram
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6
Functional Description
6.1 MPU Interface
6.1.1 Selecting the Interface Type
The EM65565A IC can be operated with either parallel interface or serial interface as selected by the P/S terminal polarity to the "H" or "L", as shown in following table:
PS H : Parallel Input L : Serial Input /CS1 CS2 D/I /RD - /WR - MPUS - D7 SI D6 SCL D5~D0 (HZ)
Note: "-" Indicates that it is fixed to either "H" or "L"
Parallel Interface: When parallel interface is selected (P/S="H"), then it is possible to connect directly to either an 80-series MPU or a 68-series MPU by selecting the MPUS terminal to either "H" or "L".
MPUS L: 80-series MPU H: 68-series MPU /CS1 CS2 D/I /RD E /WR R/W D7~D0
Identification of data bus signals through a combination of D/I, /RD (E), /WR (R/W) signals as shown in the following table:
68-Series D/I 1 1 0 0 R/W 1 0 1 0 0 1 0 1 80-Series /RD /WR 1 0 1 0 Function Reads the display data Writes the display data Read status Write control data (command)
Serial Interface: When the chip is in an active state (/CS1="L" and CS2="H") the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the SI pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the 8th serial clock for the processing. The D/I input is used to determine whether the serial data input is display data (D/I="H") or command data (D/I="L"). The D/I input is read and used for detection every 8th rising edge of the serial clock after the IC becomes active.
/CS1 CS2 SI SCL
1 2 3 4 5 6 7 8 9 10 11 12 13
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3
D/I
Fig. 2 Serial Interface Signal Chart 12 * Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
NOTE 1. 2. 3. When the IC is not active, the shift registers and counter are reset to their initial states. Reading is not possible while in serial interface mode. Caution is required on the SCL signal when it comes to line-end reflections and external noise. It is recommended that operation be rechecked on the actual equipment.
6.1.2 Chip Select
The EM65565A IC has two chip select terminals: /CS1 and CS2. The MPU interface or the serial interface is enabled only when /CS1="L" and CS2="H". When chip select is inactive, D0 to D7 enter a high impedance state and the D/I, /RD, and /WR inputs are inactive. When serial interface is selected, the shift register and the counter are reset.
6.1.3 Accessing the DDRAM and the Internal Registers
To match the operation frequencies between the MPU and DDRAM or internal register, the EM65565A performs a sort of LSI-LSI pipelining via the bus holder attached to the internal data bus. When the MPU writes data to the DDRAM, once the data is stored in the bus holder, it is written to the DDRAM before the next data write cycle. Moreover, when the MPU reads the DDRAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the DDRAM. It should be noted that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated during the second time data read. Thus, a dummy read is required whenever an address setup or write cycle operation is conducted. This relationship is shown in Figure 3.
6.1.4 Busy Flag
The busy flag is output to pin D7 by a read status command. When the busy flag is "1" it indicates that the EM65565A IC is executing its internal operations, and any command other than status read is rejected during this time. If the cycle time (tCYC) is maintained, this flag need not be checked before each command. This makes it possible for vast improvements in MPU processing capabilities.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
/WR MPU DATA BUS Holder /WR N
Latch
N+1 N N+1
N+2 N+2
N+3 N+3
Internal Timing
/WR MPU RD DATA N N+1 N+2 N+3
Address Preset Read Signal
Internal Timing
Column Address BUS Holder
Increment N+1 N Address Set #n Dummy Read n Data Read #n
N+2 n+1 Data Read #n+1 n+2
Fig. 3 DDRAM Read Sequence
6.1.5 Page Address Circuit
The page address of the DDRAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 is the page for the RAM region used only by the static indicators, and only the display data D0 is used.
6.1.6 Line Address Circuit
The line address circuit specifies the line address corresponding to the common output when the DDRAM contents are displayed. Using the display start line address set command, the normally the top line of the display can be specified (which is the COM0 output when the common output mode is normal, and the COM63 output for the EM65565A when the common output mode is reversed. The display area is a 65 lines area for the EM65565A from the display start line address. If the line address is changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.
14 * Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
6.1.7 Column Addresses Circuit
The DDRAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the column address increment stops with 83H. Since the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to specify both the page address and the column address. Furthermore, the ADC command can be used to reverse the relationship between the DDRAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized.
6.1.8 Display Data RAM (DDRAM)
The DDRAM stores the dot data for the display, and it has 65x132 bits. It is possible to access the desired bit by specifying the page address and the column address. The D7 to D0 display data from the MPU corresponds to the LCD common direction. There are few constraints at the time of display data transfer when multiple EM65565A ICs are used. Hence, display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the DDRAM is accessed asynchronously during a Liquid Crystal Display, it will not cause adverse effects on the display (such as flickering).
D0 D1 D2 D3 D4
1 0 0 0 1
0 1 0 1 0
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
COM0 COM1 COM2 COM3 COM4
Display Data RAM
Liquid Crystal Display
Fig. 4 Display Data RAM and Liquid Crystal Display Diagrams
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
Page Address Data D3 D2 D1 D0 D0 D1 D2 0 0 0 0 D3 D4 D5 D6 D7 D0 D1 D2 0 0 0 1 D3 D4 D5 D6 D7 D0 D1 D2 0 0 1 0 D3 D4 D5 D6 D7 D0 D1 D2 0 0 1 1 D3 D4 D5 D6 D7 D0 D1 D2 0 1 0 0 D3 D4 D5 D6 D7 D0 D1 D2 0 1 0 1 D3 D4 D5 D6 D7 D0 D1 D2 0 1 1 0 D3 D4 D5 D6 D7 D0 D1 D2 0 1 1 1 D3 D4 D5 D6 D7 1 0 0 0 D0
D0=1 D0=0
Line Address Page 0
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COMMON OUTPUT COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
START
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7 Page 8
S127 04 7F 81 02 80 03 7F 04 S128 03 80 S130 01 82 S129 02 81
83 00
82 01
Fig. 5 Display Data RAM
6.1.9 Display Data Latch Circuit
The display data latch circuit temporarily stores the display data that is output to the liquid crystal driver from the DDRAM. Since the display normal/reverse status, display On/Off status, and display all points On/Off commands control only the data within the latch, they do not change the data within the DDRAM itself.
16 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
S131 00 83
ADC
S0
S1
S2
S3
S4
EM65565A
65 COM/132SEG STN LCD Driver
6.1.10 Oscillator Circuit
This is an RC-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S="H" and DCLKS="H". When DCLKS="L" the oscillation stops, and the display clock is input through the DCLK terminal.
6.1.11 Display Timing Generator Circuit
The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading from the display data liquid crystal driver circuits is completely independent of accesses to the DDRAM by the MPU. Consequently, even if the DDRAM is accessed asynchronously during a Liquid Crystal Display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave from using a two-frame alternating current drive method, as shown in Figure 6, for the liquid crystal drive circuit.
64 65 1 2 3 4 63 64 65 1 2 3
CL FR COM0
DCLK
COM1 RAM DATA SEGn
V0 V1 V4 Vss V0 V1 V4 Vss
V0 V2 V3 Vss
Fig. 6 Drive wave from a two-frame AC drive method
When several EM65565A ICs are used, the slave ICs must be supplied with display timing signals (FR, DCLK, /BCT) from the master ICs. Operating mode descriptions are shown in the following table:
Master (M/S = "H") Slave (M/S = "L") Note: O : Output Operating Mode Internal oscillator circuit is enabled (DCLKS="H") Internal oscillator circuit is disabled (DCLKS="L") Internal oscillator circuit is enabled (DCLKS="H") Internal oscillator circuit is disabled (DCLKS="L") I : Input NOTE When the EM65565A is used for the master/slave configuration, each of the DCLKS pins is set to the same level together. Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
FR O O I I
DCLK /BCT O O I O I I I I
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6.1.12 Common Output Status Select Circuit
For the EM65565A IC, the COM output scan direction can be selected by the common output status select command (See Table below). Consequently, constrains in the IC layout at the time of LCD module assembly can be minimized.
Status Normal Reverse COM Scan Direction COM0 COM63 COM63 COM0
6.1.13 LCD Driver Circuits
These are 197 channels that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 7 shows examples of the SEG and COM output waveform.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM63
SEG0 SEG1 SEG2 SEG3 SEG4
FR
COM0
COM1
SEG0
Fig. 7 SEG and COM Output Waveform
6.1.14 Power Supply Circuits
The power supply circuits have low-power consumption and can generate the voltage levels required for the liquid crystal drivers. They comprise of Booster (step-up voltage) circuits, Voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuit can turn the Booster circuits, the voltage regulator circuits and the voltage follower circuit On or Off independently through the use of the Power Control Set command. Hence, it is possible to make both external and internal power supplies function in parallel.
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Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
6.1.15 Step-up Voltage Circuit
Using the step-up voltage circuit built-in within the EM65565A IC, it is possible to produce a five times step-up, a four times step-up, a three times, and a two times step-up of the VCI voltage levels. The step-up voltage relationship is shown in Figure 8.
VDD VCI VDD VCI VDD VCI VDD VCI
VCI VSS VOUT CAP4+ CAP3+ CAP1CAP1+ CAP2+ CAP2C + C +
VCI VSS VOUT CAP4+ CAP3+ CAP1CAP1+ CAP2+ CAP2C + + C C +
VCI VSS VOUT CAP4+ CAP3+ CAP1CAP1+ CAP2+ CAP2+ C C + + C C +
VCI VSS VOUT CAP4+ CAP3+ CAP1CAP1+ CAP2+ CAP2+ C C + + C C +
+ C -
VOUT=2xVCI
VOUT=3xVCI
VOUT=4xVCI
VOUT=5xVCI
Fig. 8 Step-up Voltage Circuits
6.1.16 Voltage Regulator Circuit
The step-up voltage generated at VOUT, outputs the LCD driver voltage V0 through the voltage regulator circuit. Since the EM65565A IC has an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V0 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. (a) Using the V0 voltage regulator internal resistors Through the use of the V0 voltage regulator internal resistors and the electronic volume function, the liquid crystal power supply voltage V0 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the LCD brightness. The V0 voltage can be calculated using equation A over the range where V0V0 = (1 +
Rb Rb )VEV = (1 + )(1 - )VREG -------------------------------------------------- (A) Ra Ra 162
QVEV = (1 -
162
)VREG
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
VOUT V0 Rb VEV VR Ra
Fig. 9 Using the V0 Voltage Regulator Internal Resistors
The is set to a particular level among the 64 possible levels through the use of the electronic volume function, depending on the data set in the 6-bit electronic volume register. The left table below shows the value for , depending on the electronic volume register settings. Rb/Ra is the V0 voltage regulator internal resistor ratio and can be set to 8 different levels through the V0 voltage regulator internal resistor ratio set command. The (1+Rb/Ra) ratio assumes the values shown in the right table below, depending on the 3-bit data settings in the V0 voltage regulator internal resistor ratio register.
D5 0 0 0 1 1 1 D4 0 0 0 1 1 1 D3 0 0 0 1 1 1 D2 0 0 0 : 1 1 1 D1 0 0 1 0 1 1 D0 0 1 0 1 0 1 63 62 61 : 2 1 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 1+(Rb/Ra) Ratio 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 VREG External Input 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
The VREG is affected by Temperature interference, which is cause by a semiconductor material character. The Temperature coefficient is about -0.3% / C.
20 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver (b) Using an External Resistance The liquid crystal power supply voltage V0 can also be set without using the V0 voltage regulator internal resistors but by adding resistors Ra' and Rb'. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the LCD by controlling the LCD power supply voltage V0 through commands. In the range where V0V5 = (1 +
Rb' Rb' )VEV = (1 + )(1 - )VREG ' ---------------------------------------------- (B) Ra' Ra' 162
QVEV = (1 -
162
)VREG
VOUT V0 Rb'
VEV
VR Ra'
Fig. 10 Using External Resistance
6.1.17 Liquid Crystal Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3 and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3, and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for the EM65565A can be selected.
6.1.18 Power Supply Control Circuit
The built-in power supply circuit of the EM65565A Series IC has very low power consumption (normal mode: /PCT = "H"). However, for LCDs or panels with large loads, this low-power supply may cause the display quality to degrade. When this occurs, setting the /PCT terminal to "L" (high power mode) can improve the display quality. It is recommended that the display be checked on the actual equipment to determine whether or not to use this mode. Moreover, if improvements to the display are inadequate even after high power mode has been set, then it is necessary to externally add a liquid crystal drive power supply.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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6.1.19 Internal Power Supply Shutdown Command Sequence
This sequence is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply OFF. Step 1: Display OFF Step 2: Display all points ON Step 3: Internal power supply OFF
6.1.20 Reference Circuit Example
Figure 11 shows the reference circuit examples: 1. When all of the step-up circuit, voltage regulating circuit, V/F circuit, and the voltage regulator internal resistor are used, as shown in Fig 11-(a). 2. When all of the step-up circuit, voltage regulating circuit, V/F circuit, and the voltage regulator internal resistor are not used, as shown in Fig 11-(b). 3. When the voltage regulator circuit, V/F circuit and the V0 voltage regulator internal resistor are used, as shown in Fig 11-(c). 4. When the voltage regulator circuit and V/F circuit are used, and the V0 voltage regulator internal resistor is not used, as shown in Fig 11-(d). 5. When the V/F circuit is used, as shown in Fig 11-(e). 6. When any internal LCD power supply circuit is not used, as shown in Fig 11-(f).
VDD
VDD
IRS
M/S VCI VSS
C A
IRS
M/S VCI VSS
C A
VOUT CAP4+ CAP3+
C A
VOUT CAP4+ CAP3+
C A
CAP1C A
CAP1C A
CAP1+ CAP2+
C A
CAP1+ CAP2+
C A
CAP2VR
C B
CAP2VR
C B C B R a R b C B C B C B
V0 V1 V2 V3
V0 V1
C B C B
V2 V3
C B C B
V4
V4
(a)
(b)
Fig. 11-(a~b) Reference Circuit Examples
22 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
VDD VDD
IR S
M /S VCI VSS VOUT C AP4+ C AP3+
CA
IR S
M /S VCI VSS
E x te rn a l Power S u p p ly
VOUT C AP4+ C AP3+
E x te rn a l Power S u p p ly
CA
CAP1CA
CAP1CA
C AP1+ C AP2+
CA
C AP1+ C AP2+
CA
CAP2VR
CB
CAP2Ra
VR V0
CB
Rb CB
V0 V1
CB
CB
V1
CB
V2
CB
V2
CB
V3
CB
V3
CB
V4
V4
(c)
(d)
VDD
VDD
IR S
M /S VCI VSS VOUT C AP4+ C AP3+ C AP1C AP1+ C AP2+ C AP2VR
CB
IR S
M /S VCI VSS VOUT C AP4+ C AP3+ C AP1C AP1+ C AP2+
E x te rn a l Power S u p p ly
C AP2VR V0 V1 V2 V3 V4 E x te rn a l Power S u p p ly
V0
CB
V1
CB
V2
CB
V3
CB
V4
(e)
(f)
Fig. 11-(c~f) Reference Circuit Examples
Examples of shared reference settings, with V0 varied between 8V and 12V.
Item CA CB Set Value 1.0 - 4.7 0.47 - 1.0 F F
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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NOTE 1. 2. 3. Since the VR terminal input impedance is high, use short leads and shielded lines. CA and CB are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Recommend X5R or X7R type Capacitors for CA and CB.
6.1.21 Reset Circuit
When the /RST input falls to "L", these LSI reenter their default state. The default settings are shown below: 1. Display OFF 2. Normal display 3. ADC select: normal (ADC command D0 = 0) 4. Power control resistor: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias ratio: 1/9 bias 7. Read-modify-write OFF 8. Static indicator OFF: Static indicator register: (D1, D2) = (0, 0) 9. Display start line set to first line 10. Column address set to address 0 11. Page address set to page 0 12. Common output status normal 13. V0 voltage regulator internal power supply ratio set mode clear 14. V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0) 15. Electronic volume register set mode clear 16. Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0) 17. Test mode clear When the reset command used only default settings, items 7 to 15 above are put into effect. The /RST terminal is connected to the MPU reset terminal, causing this IC to reinitialize simultaneously with the MPU. During power on, it is necessary to reinitialize using the /RST terminal. In the EM65565A, if the internal liquid crystal power supply circuit is not used, then it is necessary to apply an "L" signal to the /RST terminal when the external liquid crystal power supply is applied. Even though the oscillator circuit operates while the /RST terminal is in "L", the display timing generator circuit is stopped, and the DCLK, FR, FRS, and /BCT terminals are fixed to "H". There is no influence on the D0 to D7 terminals.
24 * Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
7
Commands
Command Command Code D/I /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 010 010 010 010 010 001 110 101 010 010 010 010 010 010 010 010 010 010 010 010 010 101 010 010 010 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0 0 0 1 0 0 0 1 0 1 1 1 D Functions LCD display ON/OFF D=0: OFF, D=1: ON Sets the display RAM display start line address Sets the display RAM page address Sets the most 4 bits of the display RAM column address Sets the least 4 bits of the display RAM column address Reads the status data Writes to the display RAM Reads from the display RAM 0 1 1 0 0 1 0 0 1 0 1 0 1 1 D D D D 0 0 0 Sets the display RAM address SEG output correspondence D=0: normal, 1: reverse Sets the LCD display normal/reverse D=0: normal, 1: reverse Display all points D=0: normal display D=1: all points ON Sets the LCD drive voltage bias ratio D=0: 1/9, D=1: 1/7 Column address only increment at write: +1 Stop read-modify-write Internal reset Select COM output scan direction D=0: normal direction D=1: reverse direction Select internal power Supply operating mode Select internal resistor ratio mode Set the V0 output voltage electronic volume register D=0: OFF, D=1: ON Set the flashing mode Display OFF and display all points ON compound command Command for non-operation Command for IC test. Don't use this command
Display ON/OFF Display start line set Page address set Column address set upper bit Column address set lower bit Status read Display data write Display data read ADC select Display normal/reverse Display all points ON/OFF LCD bias set Read-modify-write End Reset Common output mode select Power control set V0 voltage regulator internal resistor ratio set Electronic volume mode set Electronic volume Register set Static indicator ON/OFF Static indicator register set Power saver NOP Test
Display start address 1 0 0 1 1 0 Page address Most column address Least column address 0 Write data Read data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 D 1 0 0 0 0 0
Status
*
*
*
Operating mode Resistor ratio 0 0 1
*
1
* Electronic volume value
0 1 0 1 1 0 D
*
1 1 1 1
*
0 0 1 1
*
1 1 1 1
*
0 0 0 1
*
1 0 0
*
1 1 0
Mode 1 0 1 0 1 1
*
*
*
*
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
7.1 Display ON/OFF
This command turns the display on and off. When the display OFF command is executed during a display all points ON mode, power saver mode is entered. (AEH, AFH)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D
Note: D = 0: Display is turned OFF D = 1: Display is turned ON
7.2 Set Display Start Line
This command specifies a line address, thus, marking the display line that corresponds to C0. (40H to 7FH)
D/I 0 /RD 1 /WR(R/W) 0 D7 0 D6 1 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
A5 0 0 1 1
A4 0 0 1 1
A3 0 0 1 1
A2 0 0 1 1
A1 0 0 1 1
A0 0 1 0 1
Line Address 0 1 62 63
7.3 Set Column Address
This command specifies a DDRAM column address. When the column address is set, it is split into two parts (the upper 4-bits and the lower 4-bits). The column address is automatically incremented by 1 each time the MPU accesses from the set address to the DDRAM. Therefore, the MPU can access the data continuously. The column address stops to be incremented at address 131 (83H), and the page address is not changed continuously. Upper bits (10H to 18H), Lower bits (00H to 0FH)
D/I 0 /RD 1 /WR(R/W) 0 Upper bits Lower bits D7 0 0 D6 0 0 D5 0 0 D4 1 0 D3 A7 A3 D2 A6 A2 D1 A5 A1 D0 A4 A0
A7 0 0 0 1 1 1 26 *
A6 0 0 0 0 0 0
A5 0 0 0 0 0 0
A4 0 0 0 0 0
A3 0 0 0 0 0 0
A2 0 0 0 0 0 0
A1 0 0 1 0 1 1
A0 0 1 0 1 0 1
Line Address 0 1 2 129 130 131
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
7.4 Set Page Address
This command is used to specify a page address equivalent to a row address for MPU access to the DDRAM. (B0H to B8H)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 0 D5 1 D4 1 D3 A3 D2 A2 D1 A1 D0 A0
A3 0 0 0 1
A2 0 0 1 0
A1 0 0 1 0
A0 0 1 1 0
Page Number 0 1 7 8
7.5 Select ADC
This command specifies a segment driver direction. The column address is automatically incremented by 1 each time a read or a write display data operation is performed. (A0H, A1H)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
Note: D=0 clockwise output (forward) S0 (00H) S131 (83H) D=1 counterclockwise output (reverse) S0 (83H) S131(00H)
7.6 Write Display Data
Write data from the data bus into the DDRAM. The column address is automatically incremented by "1" after a write operation.
D/I 1 /RD 1 /WR(R/W) 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data
7.7 Read Display Data
Read data from the DDRAM onto the data bus. The column address is automatically incremented by "1" after a read operation. When serial interface is used, reading the display data becomes invalid.
D/I 1 /RD 0 /WR(R/W) 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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65 COM/132SEG STN LCD Driver
7.8 Read Status
D/I 0 /RD 0 /WR(R/W) 1 D7 Busy D6 D5 D4 D3 0 D2 0 D1 0 D0 0 ADC ON/OFF Reset
Busy: the busy bit indicates whether the driver accepts instruction or not Busy=0: The driver will accept new instruction Busy=1: No new instruction will be accepted ADC: ADC=0: Reverse (column address 131-n segment driver n) ADC=1: Normal (column address n segment driver n) ON/OFF: indicates the current status of the display ON/OFF=0: Display ON ON/OFF=1: Display OFF Reset: indicates whether the driver is executing a hardware or software reset or if it is in normal operation mode Reset=0: Normal operation Reset=1: Currently executing a reset instruction
7.9 Read-Modify-Write
This instruction supersedes the column address register auto-increment after a data read. The current contents of the column address register are saved. This mode remains active until an "End" instruction is received. When the "End" instruction is entered, the column address returns to the initial mode address prior to the input of the Read-modify-Write instruction. This function can reduce the MPU load when data change is repeated at a specific display area (such as cursor blinking). Any instruction can be used except for the column address set instruction which cannot be used. (E0H)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
7.10 End
This instruction cancels the read-modify-write instruction, returning the column address to the initial mode address. (EEH)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
28 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
7.11 Reset
This instruction initializes the display data line register, hence, the column address, the page address counter, the V0 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and read-modify-write mode and test mode are released. It does not affect the contents of the DDRAM. When the power supply is turned on, a reset signal is entered in the /RST pin. The reset instruction cannot be used in place of the reset signal. (E2H)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
7.12 Display All Points ON
This command makes it possible to force all display points ON regardless of the content of the DDRAM. The contents of the DDRAM are maintained when this is done. (A4H, A5H)
D/I /RD /WR(R/W) D7 0 1 0 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D Setting D=0: Normal display D=1: Display all point ON
7.13 Display Normal/Reverse
This command can reverse the lit and unlit display without overwriting the contents of the DDRAM. When this is done the DDRAM contents are maintained. (A6H, A7H)
D/I /RD /WR(R/W) D7 0 1 0 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D Setting D=0: Normal (RAM data "H" LCD ON) D=1: Reverse (RAM data "L" LCD ON)
7.14 LCD Bias Set
This command specifies the voltage Bias ratio for the LCD (A2H, A3H)
D/I /RD /WR(R/W) D7 0 1 0 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 D Setting D=0 : 1/9 Bias D=1 : 1/7 Bias
7.15 Common Output Mode Select
This command can select the scan direction of the common output terminal
D/I /RD /WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 Setting D=0 : Normal COM0COM63 D=1 : Reverse COM63COM0 * 29
0
1
0
1
1
0
0
D
*
*
*
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
Note: * stands for don't care
7.16 Power Controller Set
This command sets the function of power supply circuit
D/I /RD /WR(R/W) D7 D6 D5 D4 D3 D2 D1 D0 Setting Voltage Follower Circuit D0=0: OFF, D0=1: ON Voltage Regular Circuit D1=0: OFF, D1=1: ON Booster Circuit D2=0: OFF, D2=1: ON
0
1
0
0
0
1
0
1
D2
D1
D0
7.17 V0 Voltage Regulator Internal Resistor Ratio Set
This command sets the V0 voltage regulator internal resistor ratio. (20H, 27H)
D/I /RD /WR(R/W) D7 0 1 0 0 D6 0 D5 1 D4 0 D3 0 D2 0 1 D1 0 1 D0 0 1 1+Rb/Ra ratio Small Large
7.18 Electronic Volume
This command is used in pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other Electronic Volume Mode Set: When this command is input, the electronic volume register set command is enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used.
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
Electronic Volume Register Set: This command specifies the LCD drive voltage V0 to assume one of the 64 Voltage levels. When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0).
D/I /RD /WR(R/W) D7 0 1 0 D6 D5 0 1 D4 0 1 D3 0 1 D2 0 1 D1 0 1 D0 1 1 V0 Small Large
*
*
Note: * stands for don't care
30 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
7.19 Static Indicator
This command controls the static drive system indicator display. This is used when one of the static indicator LCD drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. Static Indicator ON/OFF: When the static indicator ON command is entered, the static indicator register set command is enabled.
D/I /RD /WR(R/W) D7 0 1 0 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 D Static Indicator D=0: OFF D=1: ON
Static Indicator Register Set:
D/I /RD /WR(R/W) D7 D6 D5 D4 D3 D2 D1 0 0 1 1 Note: * stands for don't care D0 0 1 0 1 Indicator Display State OFF Blinking at approximately 0.5 second Blinking at approximately 1 second Constantly ON
0
1
0
*
*
*
*
*
*
7.20 Power Save
The power save mode is entered when the display all points ON is performed while in display OFF mode. The power save mode includes the sleep mode and the standby mode. The sleep mode is entered when the static indicator is OFF, and the standby mode is entered when the static indicator is ON. This mode is cleared by the command display all points OFF. In sleep mode, all operations in the LCD display system stops, and remains in that state as long as there are no accesses from the MPU. In sleep mode operation, the oscillator circuit, the LCD power supply circuit, and all LCD driver circuits are halted. In standby mode operation, the duty LCD display system operations are halted and only the static driver system for the indicator continues to operate, providing the minimum required current consumption for the static driver. In sleep mode operation, the LCD power supply circuit and the duty system LCD drive circuits are halted. The static drive system does not operate and the oscillator circuit continues to operate.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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EM65565A
65 COM/132SEG STN LCD Driver
Static Indicator OFF (D7-D0)=AC (Hex)
Static Indicator ON (D7-D0)=AD (Hex) (D7-D0)=X0~X3H (Hex)
1.Display OFF (D7-D0)=AE (Hex) 2.Display All Points ON (D7-D0)=A5 (Hex)
1.Display OFF (D7-D0)=AE (Hex) 2.Display All Points ON (D7-D0)=A5 (Hex)
Sleep Mode
Stanby Mode
1.Normal Display Mode (D7-D0)=A4 (Hex) 2.Static Indicator ON (D7-D0)=AD (Hex) (D7-D0)=X0~X3H (Hex)
Normal Display Mode (D7-D0)=A4 (Hex)
Stanby Mode Cancel Sleep Mode Cancel
X : don't care
Fig. 12 Power Saving Method Flow Diagram
7.21 NOP
Non-operation command (E3H)
D/I 0 /RD 1 /WR(R/W) 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1
7.22 Test
This command is for IC testing purposes. It can be cleared by applying an "L" signal to /RST input though the reset command or by using a NOP.
D/I /RD /WR(R/W) D7 1 D6 1 D5 1 D4 1 D3 D2 D1 D0 0 1 0 Note: * stands for don't care
*
*
*
*
32 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver Initialization:
Turn on the system power setting / RST pin to "L"
When power is stabilized
When the built-in power is used immediately after turning on the power
Setting the /RST pin to "H" (Initialized state )
When the built-in power is not used immediately after turning on the power
LCD bias setting, ADC selection, common output state selection
Power Saver
Internal resistor ratio and electronic volume control setting
LCD bias setting, ADC selection, common output state selection
Power Control Setting
Internal resistor ratio and electronic volume control setting
Initialization completed
Power Saver OFF
Power Control Setting
Initialization completed
Fig. 13 Initialization Process Flow Diagram
The Relationship between oscillator frequency fOSC, display clock frequency fCL and the LCD frame rate frequency fFR, is shown in the following table:
Oscillator Circuit When the internal oscillator circuit is used (DCLKS="H") When the internal oscillator circuit is not used (DCLKS="L") fCL FOSC/4 External input fFR fCL/65=fOSC/(4*65) fCL/(4*65)
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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EM65565A
65 COM/132SEG STN LCD Driver
8
Absolute Maximum Ratings
Unless otherwise noted, VSS = 0V
Parameter Power Supply Voltage Power supply voltage Power supply voltage Input voltage Output voltage Operating temperature Storage temperature TCP COG Symbol VDD VOUT, V0 V1, V2, V3, V4 VIN VO TOPR TSTR Conditions -0.3 to +4.0 -0.3 to 12 -0.3 to V0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -30 to +85 -55 to +100 -55 to +125 Unit V V V V V C C
Notes and Cautions 1. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that V0V1V2V3V4VSS. Permanent damage to the LSI may result if the LSI is used outside the absolute maximum ratings conditions. Moreover, it is recommended that in normal operation, the IC be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions, but may have a negative impact on the LSI reliability as well.
9
DC Characteristics
Item Recommended voltage Possible operating voltage Possible operating voltage Symbol Conditions & Application Pins Min. Rating Typ. Max. 3.3 3.3 12 V0 0.4V0 VDD
0.2VDD
Units
Operating Voltage (1)
Pin VDD VDD Pin VDD V0
2.7 2.4 4.5 0.6V0 VSS
Operating voltage (2)
V1, V2 V3, V4
V
High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Output leakage current LCD driver ON resistor 34 *
VIHC VILC VOHC VOLC ILI ILO RON
Pin D/I, D0-D7, /RD, /WR, /CS1, CS2, DCLKS, DCLK, FR, M/S, MPUS, P/S, /BCT, /RST, IRS, /PCT
IOH=-0.5mA IOL=0.5mA
0.8VDD
VSS
0.8VDD
Pin D0-D7, FR, FRS, /BCT, DCLK
VDD
0.2VDD
VSS -1.0 -3.0 3.2
VIN=VDD or VSS Pin D/I, /RD, /WR, /CS1, CS2, DCLKS, M/S, MPUS, P/S, /RST, IRS, /PCT Pin D0-D7, FR, FRS, /BCT, DCLK Ta=25C, Pin COMn & SEGn V0=8V, |V|=0.1V
1.0 3.0 5.4
A
k
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
Item Static consumption current Output leakage current Sleep mode current consumption Standby mode current consumption Display ON current consumption Display OFF current consumption Input terminal capacitance
Oscillator Frequency
Symbol ISSO I0Q IDDS1 IDDS2 IDDS3 IDDS4 CIN fOSC fDCLK
Conditions & Application Pins Min. Pin VSS, VSS2 V0=16V, Pin V0 VDD= 3V, 4 times booster VDD= 3V, 4 times booster VDD= 3V, 4 times booster, All on pattern, Display on VDD= 3V, 4 times booster, All on pattern, Display off Ta=25C, f=1MHz Ta=25C Pin DCLK With double 18 18 2.4 2.4 2.4 60
Rating Typ. 0.01 0.01 0.01 4 220 80 5.0 22 22 Max. 5 15 5 8 290 100 8.0 26 26 3.5 3.5 3 2.4 12 6 4.5 12 12
Units
A
pF kHz
Internal oscillator External input
Input voltage
VCI
With triple With quad With five times
Supply step-up output voltage Voltage follower circuit operating voltage Voltage follower circuit operating voltage Base voltage
VOUT VOUT V0 VREG
Pin VOUT Pin VOUT Pin V0 Ta=25C
V
2.128 2.15 2.172
NOTE 1. 2. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that V0V1V2V3V4VSS. Unless otherwise specified, VSS = 0 V, VDD = 3.0 V 10%, Ta = -30C to 85C Dynamic Current Consumption (1) during Display, with the Internal Power Supply OFF is Current consumed by total ICs when an external power supply is used.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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EM65565A
65 COM/132SEG STN LCD Driver
10 Timing Diagram
10.1 System Bus Read/Write Timing I (80-Series MPU)
D/I TAW80 /CS1 CS2="1" TCYC80 /WR, /RD TCCLR,TCCLW TDS80 D0~D7 (write) D0~D7 (read) TACC80 TOH80 TCCHR,TCCHW TDS80 TAH80
Fig. 14 System Bus Read/Write Timing Diagram for 80-Series MPU
(VDD=2.4V to 3.3V, Ta=-30 to 85C)
Item Address hold time Address setup time System cycle time
Control L pulse width (/WR) Control L pulse width (/RD) Control H pulse width (/WR) Control H pulse width (/RD)
Signal D/I D/I /WR /RD /WR /RD D0 to D7
Symbol TAH80 TAW80 TCYC80 TCCLW TCCLR TCCHW TCCHR TDS80 TDH80 TACC80 TOH80 NOTE
Condition
Rating Min 0 0 300 60 120 60 60 40 15 -10 Max ---------140 100
Units ns ns ns ns ns ns ns ns ns ns ns
Data setup time Address hold time /RD access time Output disable time
CL=100pF
1.
The input signal rise time and fall time (TR, TF) is specified at 15 ns or less. When the system cycle time is extremely fast, (TR+TF)(TCYC80-TCCLW-TCCHW) for (TR+TF)(TCYC80-TCCLR-TCCHR) are specified. All timing is specified using 20% and 80% of VDD as the reference. TCCLW and TCCLR are specified as the overlap between /CS1 being "L" (CS2="H") and /WR and /RD being at the "L" level.
2. 3.
36 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
10.2 System Bus Read/Write Timing (68-Series MPU)
D/I R/W TAW68 /CS1 CS2="1" TEWHR,TEWHW E TDS68 D0~D7 (write) D0~D7 (read) TACC68 TOH68 TCYC68 TEWLR,TEWLW TAH68
TDH68
Fig. 15 System Bus Read/Write Timing Diagram for 68-Series MPU
(VDD=2.4V to 3.3V, Ta=-30 to 85C)
Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H Read Pulse Time Write Enable L Pulse Read Time Write Signal D/I D/I D0 to D7 Symbol TAH68 TAW68 TCYC68 TDS68 TDH68 TACC68 TOH68 TEWHR TEWHW TEWLR TEWLW NOTE 1. The input signal rise time and fall time (TR, TF) is specified at 15 ns or less. When the system cycle time is extremely fast, (TR+TF)(TCYC68-TEWLW-TEWHW) for (TR+TF)(TCYC6-TEWLR-TEWHR) are specified. All timing is specified using 20% and 80% of VDD as the reference. TEWLW and TEWLR are specified as the overlap between /CS1 being "L" (CS2="H") and E. Condition Rating Min 0 0 300 40 15 -10 120 60 60 60 Max -----140 100 ----Units ns ns ns ns ns ns ns ns ns ns ns
CL=100pF
E E
2. 3.
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
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EM65565A
65 COM/132SEG STN LCD Driver
10.3 Serial Interface
TCSS TSAS TCSH TSAS
/CS1 CS2="1" D/I
TSCYC
SCL
TSLW TF TSDS
TSHW TR TSDH
SI
Fig. 16 Serial Interface Timing Diagram
(VDD=2.4V to 3.3V, Ta=-30 to 85C)
Item Serial Clock Period SDCLK "H" pulse width SDCLK "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SDCLK time Signal Symbol TSCYC TSHW TSLW TSAS TSHA TSDS TSDH TCSS TCSH Condition Rating Min 250 100 100 150 150 100 100 150 150 Max - - - - Units ns ns ns ns ns ns ns ns ns
SCL D/I SI CS
1. The input signal rise and fall time (TR, TF) are specified at 15 ns or less. 2. All timing is specified using 20% and 80% of VDD as the standard.
10.4 Display Control Output Timing
DCLK (OUT)
TDFR
FR
Fig. 17 Display Control Output Timing Diagram
38 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver (VDD=2.4V to 3.3V, Ta=-30 to 85C)
Item FR delay time Signal Symbol FR TDFR Condition CL=50pF Rating Min. -Typ. 20 Max. 80 Units ns
10.5 Reset Timing
/RST TRW TR Internal Status During reset Reset Complete
Fig. 18 Reset Timing Diagram
VDD=2.4V to 3.3V, Ta=-30 to 85C
Item Reset time Reset "L" pulse width /RST Signal Symbol TR TRW Condition Rating Min. - 1 Typ. - - Max. 1 - Units s s
*All timing is specified with 20% and 80% of VDD as the standard.
11 Application Circuit
The MPU Interface (Reference example) The EM65565A can be connected to either 80-Series MPU or 68-Series MPU. Moreover, using the serial interface it is possible to operate the EM65565A series ICs with fewer signal lines. The display area can be enlarged by using several EM65565A Series ICs. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 80-Series MPU
VDD VCC A0 A1-A7 /IORQ MPU D0-D7 /RD /WR /RST GND /Reset D0-D7 EM65565 /RD /WR /RST MPUS P/S Decoder D/I VCC /CS1, CS2
Fig. 19 Application Circuit Diagram for the 80 Series MPU Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
* 39
EM65565A
65 COM/132SEG STN LCD Driver (2) 68-Series MPU
VDD VCC A0 A1-A15 VMA MPU D0-D7 E R/W /RST GND /Reset D0-D7 EM65565 E R/W /RST MPUS P/S Decoder D/I VCC /CS1, CS2
Fig. 20 Application Circuit Diagram for the 68 Series MPU
(3) Using the Serial Interface
VDD VCC A0 A1-A7 MPU Port 1 Port 2 /RST GND /Reset Decoder D/I VCC /CS1, CS2 EM65565 SI SCL /RST MPUS P/S VSS or VCC
Fig. 21 Application Circuit Diagram when using Serial Interface
Connections Between the LCD Drivers (Reference Example) The LCD area can be enlarged with ease through the use of multiple EM65565A ICs. Use the same equipment type. EM65565A (master) EM65565A(slave)
VDD VSS
M/S FR MASTER CL /DOF V0-V4 FR
M/S SLAVE CL /DOF V0-V4
Fig 22 Master - Slave Circuit Diagram
40 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
EM65565A
65 COM/132SEG STN LCD Driver
LCD PANEL 264*65 C1 C1 | | C65S1--------------------------S132 S133--------------------------S264 C65
VDD M/S
D/I /RST /CS1 CS2 /RD(E) /WR(R/W) D0-D7
Fig. 23 Application Circuit Diagram for the LCD Panel 264x65
12 Recommended Cog Ito Traces Resistor
Interface V0 ~ V4 CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP4+, VOUT VDD VSS /WR, /RD, /CS1, CS2, .., D7 ~ D0 /RST ITO Traces Resistance () Max = 300 Max = 100 Max = 100 Max = 50 Max = 3K 5K~10K
PORT7.0 PORT7.1 PORT7.2 PORT7.3 PORT7.4 PORT7.5 PORT6.
EM78447
D/I /RST /CS1 CS2 /RD(E) /WR(R/W) D0-D7 VDD
/BCT MASTER V0-V4 DCLK FR
/BCT V0-V4 DCLK FR
SLAVE M/S
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)
* 41
EM65565A
65 COM/132SEG STN LCD Driver
12.1 Tray Information
3X20
N 20- 424X54- 26 H
12.2 Tray Outline Dimension
Unit: mm
Symbol L1 L2 L3 T Sx Sy S X Y Dimension 50.60 45.40 45.80 4.00 13.53 7.54 15.49 10.77 1.37 Symbol Z Px Py Nx Ny N P1 P2 Dimension 0.66 11.77 1.87 3 20 60 1.76 1.60
42 *
Product Specification (V1.0) 06.06.2005
(This specification is subject to change without further notice)

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